sta

efabless/openlane2

The next generation of OpenLane, rewritten from scratch with a modular architecture

chunhuajiang/esp32-projects

ESP32 好玩、有趣、实用的项目

verilog-to-routing/tatum

Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits

OpenTimer/Parser-SPEF

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

michael-dev/ebtables-dhcpsnooping

Linux generic dhcp snooping daemon using nflog and ebtables or nftables

vlsiexcellence/Static-Timing-Analysis-Full-Course

Static Timing Analysis Full Course

vsdip/vsdflow

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys).

desmondlzy/timewalk-core

Free and extensible software that helps you keep track of you coding statistics

data2health/DREAM-Challenge

EHR DREAM Challenge

DataCoveEU/SensorThings

SensorThings work at DataCove

abranhe/sta

Parse tokens from an string into an array

filippofinke/sta-parser

⚙️ A Sensor Things API parser

masoudir/ESP_UDP_Bridge

Ceates a bidirectional link between UDP sockets and Serial port via ESP8266

StateTagApps/vue

State Tag Application in Vue.js

Brand-Frank/STM32-ALK8266

毕业设计代码【规范版本】

KAMATHAM19/RTL-to-GDSII-ASIC-design-of-Counter

The objective is to take a simple counter design from the RTL (Register Transfer Level) stage to the GDSII format using Cadence tools with a 90nm Process Design Kit (PDK).. The tools used in this process include Xcelium for simulation and coverage analysis, Genus for synthesis, Innovus for physical design, and Pegasus/PVS for physical verification.

arpit306/VSD-IAT-Sign-off-Timing-Analysis-Basics-to-Advanced

In this workshop we studied the concepts involved in STA from basics to advanced, with the help of open source STA tools and libraries.

christus/OCS_QDE

environ

DataCoveEU/INSPIRE-STA-Good-Practice

Extending INSPIRE to the IoT through SensorThingsAPI

esp32f/wifi_sta

Setup WiFi as a station and connect to AP.

MahAmorim/PetStore_Iterasys

Criação de projeto durante a semana da automação de teste de API 2021 da Iterasys

mo-tark/ezsta-search

Search Webpage for EZSTA Mappings

ogcincubator/bblocks-sta

OGC Location Building Blocks for SensorThings API

RustamC/rsta

Rust bindings for OpenSTA

StateTagApps/info

Learn to build a State Tag Application (STA).

StateTagApps/www

Public website about State Tag Applications.

ubyhzargam/OpenSTA

Timing reports are generated for various circuits using an open source tool OpenSTA. Both min and max timing reports are generated. The commands are given using a tcl script and I have used a 45nm pdk for technology mapping. The circuit is described using Verilog language. We can also generate or report power dissipated by design. MMMC is performed

venkat-devish/cart_bucket_ts

codebydant/esp32-client-server-library

This is a C program for the esp32 using ESP_IDF framework for the ap and sta wifi modules.

esp32f/wifi_apsta

Start WiFi in AP and station mode and scan APs.

ghassensta/portfolio

portfolio

panastasiadis/soc-verification-with-cad-tools

This repository is about the main project of the course "VLSI System Design". This course is part of my undergraduate studies on University of Thessally - ECE Department located in Volos, Greece.

powcoder/STA-523-Exam-1

STA 编程辅导, Code Help, WeChat: powcoder, CS tutor, powcoder@163.com

s-yk/StaTaskScheduler

Sample of TaskScheduler for STA