uart-tx
There are 14 repositories under uart-tx topic.
pConst/basic_verilog
Must-have verilog systemverilog modules
dipakgmx/ATMega_Serial
Serial communacation (USART) on the ATMega 2560 using C++ classes
MasterPlayer/axis_uart_bridge
FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol
mwbryant/uart-CI
Basic continous integration testing for verilog projects
adm1nsys/ESP32-iUART
ESP32-iUART (WROOM-32)
ColtonBeery/UART_TX
Basys 3 UART Tx for COMPE470L class
maehw/wokwi-verilog-gds-lowspeed-tiny-uart
300 baud 8N1 UART transmitter with limited character set (0x40..0x5F) loading as ASIC design
RU09342/milestone-1-communicating-with-will-byers-kvl-fan-club
milestone-1-communicating-with-will-byers-kvl-fan-club created by GitHub Classroom
xeoncesta/VHDL_Xilinx
Keyboard Scanner, UART Tx -(nandland.com), Sipo_Reg, Switch Debounce(counter), Linear Feedback Shift Register, DiceGame(2 player,win on eqauality).
arusracso/esp8266
esp8266
FunPythonEC/xl320_upy
Dynamixel xl320 support for ESP boards with micropython.
sushi0706/uart
verilog-uart
0marAmr/UART-Interface
Design of Universal Asynchronous Receiver Transmitter Interface using verilog HDL