verilog-code

There are 115 repositories under verilog-code topic.

  • EE461L_HDL_Lab_Assignment_05

  • DSP48A1

    Language:Verilog

  • Photonics-interconnects-for-Clock-routing

  • HiVeGen-Pipeline-Reproduction

    Reproduction of the HiVeGen (Hierarchical LLM-based Verilog Generation) pipeline from the paper "HiVeGen – Hierarchical LLM-based Verilog Generation for Scalable Chip Design" (arXiv:2412.05393).

    Language:SystemVerilog

  • Seven-segment-display-using-Verilog-HDL

    Design and simulation of a seven-segment display driver using Verilog HDL in Vivado, converting 4-bit binary input to 7-segment output.

  • Multiplexer-Simulation-in-Vivado

    Simulation and implementation of a 4:1 Multiplexer using Verilog HDL in Vivado with Gate-Level, Dataflow, Behavioral, and Structural modeling.

  • VERILOG-DHT-READING

    Verilog code to read DHT11

    Language:VHDL

  • Simple-CPU

    ALU, RAM and CPU (Computer Architecture)

  • Sintetizador-de-Chuck-Digital

    En el presente repositorio se encuentra toda la documentacion del proyecto general y de cada grupo de trabajo, para cada instrumento hay una carpeta destinada que contiene toda la descripcion del proceso de desarrollo, tanto a nivel de software como a nivel de hardware. Todos contaron con la tutoria del Ingeniero Electronico Johnny Cubides.

    Language:Verilog

  • ALU_74181

    A simulation of the classic 4-bit 74181 Arithmetic Logic Unit (ALU), built from scratch in Verilog.

    Language:Verilog

  • controle-microondas-verilog

    Este projeto em Verilog implementa dois módulos principais para controle de um timer, componente de um sistema de microondas. O microondas contém uma máquina de estados finitas, controle lógico para ativação, pausa, e finalização, bem como controle de potência, ativada por meio de controles físicos.

    Language:Tcl

  • VHDL

    This repository contains various Verilog implementations of fundamental digital circuits.Each module is tested with a corresponding Testbench for simulation in EDA Playground

    Language:Verilog

  • System-Verilog

    learning system verilog

    Language:SystemVerilog

  • Verilog-Projects

    Projects using Verilog Language

  • HDLBits-submissions

    Solutions for 100+ questions in HDLBits using verilog

    Language:Verilog

  • basic-VHDL

    VHDL Implementations:logic Gates, Flip-Flops, Adders, Mux, and Encoders/Decoder This repository contains VHDL implementations of essential digital circuits used in FPGA and ASIC design .This repository is useful for digital design projects and for understanding different VHDL modeling styles: behavioral, structural, and dataflow.

    Language:C

  • oficina-verilog-siecomp

    Neste repositório estão disponibilizados todos os arquivos utilizados na Oficina Introdução ao Verilog Comportamental ministrado na XXXI SIECOMP (UEFS). Além disso, estão listados múltiplos recursos para estudo da linguagem.

    Language:Verilog

  • Verilog

    These are Verilog (HDL) codes.

    Language:Verilog

  • System-Verilog-Tutorial-LFSR-

    simple system verilog example using an LFSR as the application

  • My-VHDL

    A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.

    Language:Verilog

  • Verilog_Codes

    This Repository shows the implementation and results of various codes that I write in Verilog HDL

    Language:Verilog

  • Verilog-Programming-Logic-Design-Lab

    Verilog programs in gate level, dataflow & behavioural modelling with testbenches written in intel FPGA tested with ModelSim simulator

    Language:Verilog

  • Traffic-Light-Controller

    Traffic Light Controller using Verilog done in Vivado

    Language:Verilog

  • Schoolbook-Multiplications

    This project is done in Vivado in Verilog with hardware implementation and the project is optimized Schoolbook multiplier which is much faster than the traditional ones

    Language:Verilog

  • -Karatsuba-Algorithm

    2-Term Karatsuba and 3-Term Karatsuba Algorithm on FPGAs in Vivado using Verilog with diffrent bits and with 3 diffrent method.

  • Array_Multiplier_project

    This is a 4*4 Array_Multiplier_project using Verilog HDL. This is successfully implemented on FPGA board.

    Language:Tcl

  • Verilog_Code

    Hardware Modeling Using Verilog

    Language:Verilog

  • intelunnati_adventurer

    Finite State Machine (FSM) designed to handle the movements of a Land Rover based on binary inputs. The FSM utilizes D flip-flops and combinatorial logic to transition between states and produce appropriate output signals for controlling the Land Rover's movement.

    Language:Verilog

  • most_used_modules

    most used verilog modules

    Language:Verilog

  • -

    DatenLord面试项目题-IC前端设计

  • HDL-BITS

    This Repo consists codes for some the problem statements from the HDL BITS website and can help you in your journey to learn Verilog from the scratch

  • verilog-generator

    A generator tool which creates verilog modules like, greycode encoder and decoders.

  • Verilog-HDL

    A Verilog HDL code

    Language:Verilog

  • endmodule

    Open Source Verilog Modules

    Language:Verilog

  • HDLPractice

    Repo of my HDL exercises

    Language:Verilog

  • Verilog_codes

    My ongoing practice verilog hdl codes.

    Language:Verilog