verilog-generator
There are 3 repositories under verilog-generator topic.
ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA
Verilog Generator of Neural Net Digit Detector for FPGA
donlv1997/ECC-Verilog-HDL-AutoGenerator
a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.
Sooryakiran/dotV
A library to generate parameterized Verilog code from C++. Allows you to assemble Verilog modules in C++, use C++ syntax to dynamically generate complex connections, parameterize code, and ultimately get the Verilog code automatically generated.