vexriscv

There are 10 repositories under vexriscv topic.

efabless/caravel
Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
Language:Verilog361 20 24199
chipsalliance/f4pga-examples
Example designs showing different ways to use F4PGA toolchains.
Language:Verilog277 23 16679
BLangOS/VexRiscV_with_HW-GDB_Server
VexRiscV system with GDB-Server in Hardware
Language:VHDL21 4 04
xThaid/fpga-lb
A toy L4 load balancer running on FPGA
Language:C18 1 00
jmio/ECP5_Brieysoc
Briey SoC on ECP5 (ICESugar Pro)
Language:Verilog9 3 02
jmio/testvex
Briey SoC on Sipeed Tang Primer
Language:Verilog7 1 03
mcejp/Poly94
Yet another faux-retro game system
Language:Verilog5 3 00
lnis-uofu/OpenFPGA-Softcores
Co-architect 32-bit open-source RISC-V soft-cores for improved FPGA implementations
Language:Python3 7 01
neunzehnhundert97/VexRiscv-Instruction-Framework
A small framework to simplify the creation of custom instruction for the VexRiscv.
Language:Scala2 2 01
supleed2/EIE4-FYP
Source files and notes of my Final Year Project, as part of an MEng in Electronics and Information Engineering from Imperial College London
Language:Python1 0