vivado-simulator
There are 9 repositories under vivado-simulator topic.
suoto/hdl_checker
Repurposing existing HDL tools to help writing better code
Arjun-Narula/Traffic-Light-Controller-using-Verilog
the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
esynr3z/pyhdlsim
Example of Python and PyTest powered workflow for a HDL simulation
mzh330521/SublimeLinter-contrib-xsim
Vivado Simulator (XSim) xvlog/xvhdl plugin for SublimeLinter. Linting for Verilog/SystemVerilog and VHDL.
RipperJ/VerilogExpr2NAND-NOR
Logic Expression Compiler, with Logic Minimization, to NAND/NOR Implementation
Ammar-Bin-Amir/SystemVerilog_Practice
Practice Codes of SystemVerilog Language
arhamhashmi01/Axi4-lite
This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.
amirah-sri/all_verilog
I am trying to develop my skills through daily practice and consistency.
rishz09/digital-safe-verilog
A digital safe designed in Vivado, which has a 4 digit decimal password, and is implemented on PYNQ-Z2 board and RPI-Logic board