vlsi-cad
There are 24 repositories under vlsi-cad topic.
AUCOHL/Fault
A complete open-source design-for-testing (DFT) Solution
PKU-IDEA/OpenPARF
🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
asyncvlsi/act
ACT hardware description language and core tools.
ieee-ceda-datc/RDF-2019
DATC RDF
twweeb/VLSI-Physical-Design-Automation
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
UdayaShankarS/TCL-Scripting
Examples of the TCL Scripts for different purposes and for VLSI Physical Design are provided here for your reference
paripath/cdf
Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
CaiB/GDStoSVG
Converts GDSII (IC layout database) files to SVG (Vector graphics) files.
rohankalbag/vlsi-circuit-partitioning-algorithms
Course Project - Foundations of VLSI CAD - Autumn Semester 2022 - Indian Institute of Technology Bombay
HsuChiChen/ncku-intro-vlsi
grayscale conversion system and simple convolution system
karthik-r-rao/VLSI_Physical_Design_Tool
A simple tool to demonstrate the physical design steps of VLSI Design Flow.
Sooryakiran/Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project
Domain Specific Hardware Accelerators - VLSI CAD Project
MayurTA/VSD-IAT_workshop
Report of the contents learned in the 5-day workshop by VSD regarding the open-source EDA tools in the VLSI industry
neeraj1397/A-Primer-For-Physical-Design-Automation
This repository contains python code snippets that implement several algorithms for automating the VLSI Physical Design process. This is based on the learnings from the course - EE5333W (Introduction to Physical Design Automation) at IITM.
PKU-IDEA/OpenPARF-MLCAD2023
🕹 OpenPARF-MLCAD2023: A Multi-Electrostatics Based FPGA Macro Placer Considering Cascaded Macros Groups and Fence Regions (MLCAD'23 Contest Submission)
rohankalbag/optiVLSI
A library for fast and optimized VLSI Computer-Aided-Design algorithms
RithikNambiar/vim_dotfiles
Contains vim dotfiles configured for verilog, C++ & some stuff for VLSI
the-pinbo/ROBDD
A binary decision diagram is a directed acyclic graph used to represent a Boolean function. The ROBDD is a canonical form, which means that given an identical ordering of input variables, equivalent Boolean functions will always reduce to the same ROBDD.
cuhk-eda/split-extract
Heterogeneous Feature Extraction for Split Manufactured Layouts with Routing Perturbation
FarshidKeivanian/Minimization-of-Average-Power-Consumption-in-3-Stage-CMOS-Ring-Oscillator-based-on-MSFLA-Fuzzy-MSFL
FuzzyMSFLA-Algorithm (Fuzzy adaptive optimisation method)
rohankalbag/logic-simulator
Course Assignment - Foundations of VLSI CAD - Autumn Semester 2022 - Indian Institute of Technology Bombay
Sudeep-Dhurua/verilog-to-gate-level-synthesis
This Project consist of a first level synthesizer. It will take a Hardware-Description written in Verilog standard (or ****.v) file and convert it into gate level netlist.
the-pinbo/BooleanCalculator
boolean calculator engine using urp
the-pinbo/EC704-VLSI-Design-Automation
EC704 - VLSI Design Automation