vyges

There are 7 repositories under vyges topic.

  • vyges-ip-template

    🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation

    Language:Python10

  • vybox-lite

    VyBox Lite: One-click Codespaces environment for trying Vyges chip/IP development in your browser.

    Language:JavaScript1

  • hilbert-transformer

    A fully pipelined digital Hilbert transformer IP block for DSP applications including single sideband modulation, amplitude/phase detection, and quadrature signal processing. Optimized for FPGA and ASIC implementations with configurable precision and maximum throughput.

    Language:SystemVerilog1

  • fast-fourier-transform-ip

    Configurable, high-performance FFT hardware IP core for ASIC/FPGA. Pipelined radix-2 DIF, 256–4096-point support, 16-bit fixed-point, double-buffered memory, APB/AXI interfaces. Optimized for throughput and low latency.

    Language:SystemVerilog

  • full-adder-ip

    A configurable full adder IP with three implementation approaches (simple XOR/AND, modular half adder, carry lookahead) following Vyges conventions. Includes comprehensive verification with SystemVerilog, UVM, and Cocotb testbenches supporting multiple simulators (Icarus, Verilator, Questa, VCS, Xcelium). Production-ready for ASIC/FPGA w/ 500MHz

    Language:Python

  • uart-controller

    A configurable UART controller IP with APB interface, FIFO support, and interrupt capabilities. Designed for SkyWater 130nm Open Source PDK with comprehensive verification and OpenLane integration.

    Language:SystemVerilog

  • vyges-metadata-spec

    📋 Vyges Metadata Specification - Standardized format for hardware IP discovery and integration

    Language:HTML