zcu102

There are 12 repositories under zcu102 topic.

  • Xilinx/Vitis-Tutorials

    Vitis In-Depth Tutorials

    Language:C1.1k45228540

  • li3tuo4/rc-fpga-zcu

    Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)

    Language:Tcl5131615

  • energymon/energymon

    A portable interface for energy monitoring utilities

    Language:C3562817

  • LaErre9/Zynq_Ultrascale_Vitis_AI_CNN_ZCU102

    Workflow for Executing CNN Networks on Zynq Ultrascale+ with VITIS AI. Detailed analysis, configuration, and execution of Convolutional Neural Networks on ZCU102 using VITIS AI, evaluating performance on the board compared to Cloud infrastructure. Developed for educational exam purposes.

    Language:Jupyter Notebook11101

  • jdibenes/zcu102_two_cameras

    ZCU102 two IMX274 camera design.

    Language:Tcl7112

  • gpanders/zynqmp-boot-apps

    Generate and install boot apps for the Zynq MPSoC device

    Language:Makefile6201

  • jdibenes/fpga_modules

    Collection of FPGA modules for video capture and processing.

    Language:Tcl2100

  • jracevedob/MPSoC_Networking

    This repository contains the source code for implementing data exchange through the SFP+ Cages of the Xilinx's Multi-processor System-on-Chip (MPSoC)

    Language:VHDL2100

  • giuseppericcio/Zynq_Ultrascale_Vitis_AI_CNN_ZCU102

    Workflow for executing CNN Networks on Zynq Ultrascale+ with Vitis AI toolchain. Detailed analysis, configuration and execution of Convolutional Neural Networks on ZCU102 using Vitis AI, evaluating performance on the board compared to Cloud infrastructure (eg. Kaggle). Developed for educational exam purposes.

    Language:Jupyter Notebook1000

  • BlaCkinkGJ/Flash-Board-Tester

    :white_check_mark: The testing program validates the BlueDBM flashboard for the ZCU102 motherboard.

    Language:C0101

  • edowson/Vitis_Embedded_Platform_Source

    Xilinx Vitis repository containing video streaming and machine learning reference designs.

    Language:C10

  • jracevedob/RLNC_MPSoC

    This directory contains the source code for implementing Random Linear Network Coding (RLNC) into Multi-Processor System-on-Chips (MPSoC). By exploiting data vectorization, we obtained latency and throughputs gains during the matrix multiplication operations.

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