turfptax/ugit

Puzzling, line 131, in add_to_tree OSError: 20

Wind-stormger opened this issue · 6 comments

Set up as required, but stopped working at the ugit.backup() :

MPY: soft reboot
boot.py
sub_path: /boot.py
/boot.py
Traceback (most recent call last):
  File "boot.py", line 9, in <module>
  File "ugit.py", line 225, in backup
  File "ugit.py", line 126, in build_internal_tree
  File "ugit.py", line 131, in add_to_tree
OSError: 20

If only executing ugit.pull_all() :

Use: like ugit.wificonnect(SSID,Password)
otherwise uses ssid,password in top of ugit.py code
Wifi Connected!!
SSID: xxx
Local Ip Address, Subnet Mask, Default Gateway, Listening on...
('192.168.11.229', '255.255.255.0', '192.168.11.1', '192.168.11.1')
boot.py
sub_path: /boot.py
/boot.py
Traceback (most recent call last):
  File "<stdin>", line 1, in <module>
  File "ugit.py", line 67, in pull_all
  File "ugit.py", line 126, in build_internal_tree
  File "ugit.py", line 131, in add_to_tree
OSError: 20

I've ran into this when there is a directory that has no files within it.

can you add print(dir_item) right after global internal_tree on line 131?

Or do you have an internal folder on the micropython board that does not contain a file?

I thought this issue was fixed but the dir_item should point us in the right direction.

Use: like ugit.wificonnect(SSID,Password)
otherwise uses ssid,password in top of ugit.py code
Wifi Connected!!
SSID: xxx
Local Ip Address, Subnet Mask, Default Gateway, Listening on...
('192.168.11.229', '255.255.255.0', '192.168.11.1', '192.168.11.1')
*NOTE:boot.py
boot.py
sub_path: /boot.py
/boot.py
*NOTE:ugit.backup
Traceback (most recent call last):
  File "<stdin>", line 1, in <module>
  File "ugit.py", line 67, in pull_all
  File "ugit.py", line 126, in build_internal_tree
  File "ugit.py", line 132, in add_to_tree
OSError: 20

Add print("*NOTE:"+dir_item) , distinction from others.

Use: like ugit.wificonnect(SSID,Password)
otherwise uses ssid,password in top of ugit.py code
Wifi Connected!!
SSID: xxx
Local Ip Address, Subnet Mask, Default Gateway, Listening on...
('192.168.11.229', '255.255.255.0', '192.168.11.1', '192.168.11.1')
*NOTE:boot.py
boot.py
sub_path: /boot.py
/boot.py
*NOTE:ugit.backup
Traceback (most recent call last):
  File "<stdin>", line 1, in <module>
  File "ugit.py", line 67, in pull_all
  File "ugit.py", line 126, in build_internal_tree
  File "ugit.py", line 132, in add_to_tree
OSError: 20

Add print("*NOTE:"+dir_item) , distinction from others.

Ah, if you add ugit.backup to the ignore_files array it should fix this.

It is possible the file is too big or not closed when this is ran. Can you tell me which board you are using and firmware version? I can try to replicate this exactly if possible.

Ah, if you add ugit.backup to the ignore_files array it should fix this.

Not fixed.

ESP32S3R2, 8M flash.
MicroPython v1.19.1

# boot.py
import ugit

ugit.backup() # good idea to backup your files!

ugit.pull_all()
user = 'Wind-stormger'
repository = 'micropython-uasycio-buzzer'

Replicated error with different message:
ESP32-C3 mini v1.19.1

First time I ran it I received this:

MemoryError: memory allocation failed, allocating 13032 bytes)

Executed the following:

  1. Closed upycraftv1.1
  2. Unplugged ESP32 Board and Plugged back in
  3. Restarted REPL through upycraftv1.1

Ran a second time and succeeded.

Known micropython memory persistence issues: REPL environment reboot + Mircopython Board Hard Reboot seems to fix.

gc.collect() works very well with object = none to fix. believe this to be a persistent memory issue that gc.collect() implementation might fix.

Will need some more testing to see if we can replicate after hard board reboot and REPL 'reset'.

Ah, if you add ugit.backup to the ignore_files array it should fix this.

Not fixed.

ESP32S3R2, 8M flash. MicroPython v1.19.1

# boot.py
import ugit

ugit.backup() # good idea to backup your files!

ugit.pull_all()
user = 'Wind-stormger'
repository = 'micropython-uasycio-buzzer'

Were you able to try again after rebooting your REPL environment and the board?

I have replicated the error but a reset of REPL and Board works every time on my end.

Also note for future. If you make any adjustments to the ugit.py file a board reset and REPL environment reset (if applicable) are almost required.