ucb-bar/riscv-mini

Issues

• Branch Instruction misaligned can't trigger exception

  #72 opened 3 months ago by SeddonShen
  0

• Store misaligned exception with the subsequent instruction's write request not flushed

  #71 opened 3 months ago by SeddonShen
  0

• How to Generate Tile.fir or Tile.mlir in generated-src after Running `make`?

  #60 opened 6 months ago by Stevengre
  1

• Problems related to asSint type conversion to verilog file (.sv)

  #66 opened 7 months ago by DIGI1919
  1

• some problem about the code of test

  #65 opened 9 months ago by DIGI1919
  2

• Is riscv-mini a single-cycle-processor?

  #63 opened 9 months ago by TDppy
  1

• Cannot run program "z3"CreateProcess error=2, system cant find the file specified

  #61 opened 9 months ago by TDppy
  1

• encountered error when performing make"firtool returned a non-zero exit code. Note that this version of Chisel (5.0.0) was published against firtool version 1.40.0."

  #62 opened 9 months ago by TDppy
  3

• NastiArbiter IO forgot wrap in IO

  #59 opened 10 months ago by ProgrammerBing
  0

• Test hexfile creation documentation

  #54 opened a year ago by ObiWanRohan
  1

• Strobe writes broken in TileTester.

  #56 opened 2 years ago by jdeters
  0

• Failed all formal verification.

  #55 opened 2 years ago by B10615053
  2

• [RFC] Upgrade to User-level ISA v2.2 and Privileged Architecture v1.10

  #29 opened 5 years ago by liangfu
  2

• Is this a BUG in TileTester.scala?

  #52 opened 2 years ago by LingZichao
  3

• Synchronous read?

  #40 opened 3 years ago by AwaniK
  1

• How do I add a new register under the source code of src, and then use GTKWave to see this register when viewing the waveform?

  #35 opened 3 years ago by fmx1233
  1

• Does this code have a bug?

  #17 opened 3 years ago by lengrongfu
  0

• Proposal to Update Project to Latest Chisel

  #23 opened 3 years ago by chick
  4

• after I use quartus II 9.0 to compile Title.v successfully, but I double click ALUArea::alu module turn on error below attached

  #4 opened 3 years ago by zhouxs1023
  1

• Generated Tile.v won't compile

  #10 opened 3 years ago by Hoblovski
  4

• Error in make command

  #16 opened 3 years ago by sagarbaba
  4

• Building priv-1.7 riscv-toolchain fails

  #19 opened 3 years ago by noureddine-as
  3

• Underlying behavior of each module

  #26 opened 3 years ago by azimgivron
  0

• Add command line argument to verilator to support very wide wires

  #31 opened 3 years ago by ucbjrl
  0

• Is this core based on zcale ?

  #36 opened 3 years ago by Askartos
  0

• make run-tests errors

  #39 opened 3 years ago by skinterqwe
  0

• riscv-mini doesn't support print and declare the float data type variable

  #14 opened 4 years ago by jtxiao82
  1

• Test directory naming simplification introduces collisions

  #32 opened 5 years ago by ucbjrl
  1

• instruction doesn't appear in spec?

  #9 opened 6 years ago by sequencer
  2

• Running simulation with other programs?

  #3 opened 7 years ago by hauhsu
  1