Verilator 4.200 2021-03-12 released

[wsnyder]

Verilator 4.200 2021-03-12 released

Major:

• Add simulation context (VerilatedContext) to allow multiple fully independent models to be in the same process. Please see the updated examples. (verilator/verilator#2660)

• Add context->time() and context->timeInc() API calls, to set simulation time. These now are recommended in place of the legacy sc_time_stamp().

Minor:

• Converted Asciidoc documentation into reStructuredText (RST) format.
• --inhibit-sim is planned for deprecation, file a bug if this is still being used.
• Fix range inheritance on port without data type (verilator/verilator#2753). [Embedded Go]
• Fix slice-assign overflow (verilator/verilator#2803) (verilator/verilator#2811). [David Turner]
• Fix interface array connection ordering broken in v4.110 (verilator/verilator#2827). [Don Owen]
• Fix or-reduction on different scopes broken in 4.110 (verilator/verilator#2828). [Yinan Xu]
• Fix MSVC++ compile error. (verilator/verilator#2831) (verilator/verilator#2833) [Drew Taussig]