veripool/verilog-perl

Issues

• Vppreproc: MMD feature

  #1672 opened 6 months ago by piecea
  2

• Failed to install Verilog::Language in Apple Mac Big Sur

  #1670 opened 6 months ago by Shang0801
  4

• Preprocessor doesn't handle one case of definition substitution properly

  #1659 opened 6 months ago by veripoolbot
  2

• vhier does not seem to inspect inside `celldefine/`endcelldefine when looking for modules

  #1685 opened 6 months ago by TJackhammer
  1

• Unexpected behavior when ending macro with ``

  #1684 opened 7 months ago by incandwo
  1

• vhier - Apply skiplist to input files and module files as well

  #1683 opened a year ago by mksoc
  2

• contassign in interface causes missing method error in Verilog::Netlist

  #1682 opened a year ago by CoreyTeffetalor
  1

• surpress include file can't open error

  #1681 opened 2 years ago by riggy2013
  5

• +define+ process function-like macros with errors.

  #1680 opened 3 years ago by elvenfarseer
  1

• Add a switch to ignore syntax error.

  #1679 opened 3 years ago by SimonZh1234
  1

• Verilog::Preproc keeps comments containing word "module" although keep_comments=0

  #1678 opened 3 years ago by adrian1001
  2

• need a parser for wire or reg signals

  #1677 opened 3 years ago by WilsonChen003
  2

• Access package import declaration(s) after file parsing

  #1676 opened 3 years ago by fischphob
  1

• parameter follows a '%' does not get replaced with obfuscated string

  #1674 opened 3 years ago by BlueStar-WhiteBirds
  2

• Verilog::Getopt doesn't recognize ${ENVVAR} system environment variables

  #1671 opened 4 years ago by henry-hsieh
  6

• `cpan install Verilog-Perl` seems to be broken

  #1667 opened 5 years ago by kevbroch
  2

• Parser didn't report macro with parsing library way

  #1669 opened 5 years ago by avendeng
  3

• Incorrect macro expansion with combination of `", ``, and embedded macro usage

  #1668 opened 5 years ago by martinwhitaker
  5

• What happened to the Verilog-Perl forum content on veripool.org?

  #1666 opened 5 years ago by mpwalsh8
  1

• Import statement script problem

  #1665 opened 5 years ago by PaulRolfe65
  5

• How to prevent link errors on parameterised module instances using vhier?

  #1664 opened 5 years ago by sjalloq
  2

• Verilog-perl Parser test fails

  #1663 opened 6 years ago by ashfak12
  14

• Getopt thinks a path is a comment

  #1610 opened 6 years ago by veripoolbot
  4

• Question: AUTOINSTPARAM use with dependent parameters

  #1662 opened 6 years ago by veripoolbot
  7

• How is ppdefine in SigParser used

  #1661 opened 6 years ago by veripoolbot
  4

• Verilog::Preproc misdocuments def_exists instead of def_params

  #1658 opened 6 years ago by veripoolbot
  4

• Question: number of whitespaces between port name & signal name + indention + tabs replacement

  #1611 opened 6 years ago by veripoolbot
  3

• perl 'make' commandline error during installation

  #1546 opened 6 years ago by veripoolbot
  2

• Question: How to prevent AUTOOUTPUT from processing wires?

  #1547 opened 6 years ago by veripoolbot
  1

• Question: not expose specific block parameter to the higher hierarchy level or expose it with its default value

  #1501 opened 6 years ago by veripoolbot
  1

• Verilog::Netlist::PinSelection->msb doesn't return anything.

  #1500 opened 6 years ago by veripoolbot
  6

• Verilog::Netlist::Cell->range doesn't return undef

  #1497 opened 6 years ago by veripoolbot
  1

• Question: Auto-indent inside macros systemverilog

  #1464 opened 6 years ago by veripoolbot
  4

• Vhier : Usage to display whole hierarchy of a pin or a port in a module or sub-module.

  #1463 opened 6 years ago by veripoolbot
  1

• Getting Error with Verilog::Netlist Module

  #1459 opened 6 years ago by veripoolbot
  5

• Question: Recursively reading files from verilog-library-flags

  #1433 opened 6 years ago by veripoolbot
  3

• Please add whatis entry in Netlist/PinSelection.pm

  #1432 opened 7 years ago by veripoolbot
  3

• Install problem from CPAN with 5.26.3/darwin-thread-multi-2level

  #1428 opened 7 years ago by veripoolbot
  3

• vrename --change misses escaped name if it is followed a newline for whitespace

  #1420 opened 7 years ago by veripoolbot
  1

• Question: how to split a port assignment to multiple lines?

  #1421 opened 7 years ago by veripoolbot
  1

• Question: Usage of '*' in verilog-library-directories

  #1395 opened 7 years ago by veripoolbot
  1

• Verilog::Std::std can return blank `std` package.

  #1394 opened 7 years ago by veripoolbot
  2

• Support ranged instances

  #1393 opened 7 years ago by veripoolbot
  1

• vhier --skiplist option not working

  #1375 opened 7 years ago by veripoolbot
  1

• vhier cannot find files in library

  #1374 opened 7 years ago by veripoolbot
  1

• memory exhausted

  #1344 opened 7 years ago by veripoolbot
  2

• Question: Indent after module open parenthesis with AUTOINST

  #1345 opened 7 years ago by veripoolbot
  1

• Constants split across lines

  #1340 opened 7 years ago by veripoolbot
  5

• Question: Using comments at end of line in AUTOINST

  #1312 opened 7 years ago by veripoolbot
  3

• Verilog::EditFiles misses module declarations where module keyword and module name are on separate lines

  #1311 opened 7 years ago by veripoolbot
  1