vyges
Building Silicon Like Software - The developer-first platform for reusable open-source hardware IP
United States of America
Pinned Repositories
vyges-ip-template
🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation
community
🏗️ Central hub for Vyges community discussions, issues, feature requests, and collaboration
vybox-lite
VyBox Lite: One-click Codespaces environment for trying Vyges chip/IP development in your browser.
hilbert-transformer
A fully pipelined digital Hilbert transformer IP block for DSP applications including single sideband modulation, amplitude/phase detection, and quadrature signal processing. Optimized for FPGA and ASIC implementations with configurable precision and maximum throughput.
mlow-codec-ip
A hardware implementation of Meta's MLow audio codec, delivering 2x better quality than Opus at 6kbps while maintaining 10% lower computational complexity. Optimized for RTC applications on resource-constrained devices.
vyges-metadata-spec
📋 Vyges Metadata Specification - Standardized format for hardware IP discovery and integration
fast-fourier-transform-ip
Configurable, high-performance FFT hardware IP core for ASIC/FPGA. Pipelined radix-2 DIF, 256–4096-point support, 16-bit fixed-point, double-buffered memory, APB/AXI interfaces. Optimized for throughput and low latency.
programmable-adc
Programmable ADC IP with Cadence PDK support, featuring behavioral models, comprehensive testbenches, and automated verification flows for mixed-signal design.
sd-card-controller-ip
pwm-controller
Configurable PWM controller with multiple channels and precise frequency control
vyges's Repositories
vyges/vyges-ip-template
🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation
vyges/vyges-metadata-spec
📋 Vyges Metadata Specification - Standardized format for hardware IP discovery and integration
vyges/mlow-codec-ip
A hardware implementation of Meta's MLow audio codec, delivering 2x better quality than Opus at 6kbps while maintaining 10% lower computational complexity. Optimized for RTC applications on resource-constrained devices.
vyges/spi-controller
SPI master controller with APB interface, multi-mode support (all SPI modes), configurable FIFO, and interrupt features for ASIC/FPGA integration.
vyges/fast-fourier-transform-ip
Configurable, high-performance FFT hardware IP core for ASIC/FPGA. Pipelined radix-2 DIF, 256–4096-point support, 16-bit fixed-point, double-buffered memory, APB/AXI interfaces. Optimized for throughput and low latency.
vyges/uart-controller
A configurable UART controller IP with APB interface, FIFO support, and interrupt capabilities. Designed for SkyWater 130nm Open Source PDK with comprehensive verification and OpenLane integration.
vyges/sd-card-controller-ip
vyges/pwm-controller
Configurable PWM controller with multiple channels and precise frequency control
vyges/programmable-adc
Programmable ADC IP with Cadence PDK support, featuring behavioral models, comprehensive testbenches, and automated verification flows for mixed-signal design.
vyges/lyra-vqdq-chiplet-ip
Lyra Codec - VQDQ
vyges/hilbert-transformer
A fully pipelined digital Hilbert transformer IP block for DSP applications including single sideband modulation, amplitude/phase detection, and quadrature signal processing. Optimized for FPGA and ASIC implementations with configurable precision and maximum throughput.
vyges/full-adder-ip
A configurable full adder IP with three implementation approaches (simple XOR/AND, modular half adder, carry lookahead) following Vyges conventions. Includes comprehensive verification with SystemVerilog, UVM, and Cocotb testbenches supporting multiple simulators (Icarus, Verilator, Questa, VCS, Xcelium). Production-ready for ASIC/FPGA w/ 500MHz
vyges/vybox-lite
VyBox Lite: One-click Codespaces environment for trying Vyges chip/IP development in your browser.
vyges/xilinx-tools
Container infra to build and use Xilinx tools
vyges/.github
vyges/vyges
vyges/community
🏗️ Central hub for Vyges community discussions, issues, feature requests, and collaboration