xboot/xfel

spi at t113-s3/D1s

ua1arn opened this issue · 3 comments

ua1arn commented

I propose two changes:

  1. slow SPI speed (50 MHz too fast sometimes).
  2. Add wait for clear start transfer bit before FIFO level check (required in user manual).
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jianjunjiang commented

50MHZ clock is no problem at all for spi nor flash

jianjunjiang commented

wait for clear start transfer bit before FIFO level check。

This is unnecessary, because there is waiting for the fifo to have enough remaining space, and then write to the fifo.

ua1arn commented

If transfer chunk size not equal to FIFO size, I got some problems if skipped transfer bit waiting.