TDM master only supports /2^n MCLK to SCLK divide ratios

[ed-xmos]

TDM master uses the XS1-friendly method of dividing MCLK by using a buffered port to generate BCLK:

static const unsigned i2s_tdm_clk_mask_lookup[5] = {
0xaaaaaaaa, //div 2
0xcccccccc, //div 4
0xf0f0f0f0, //div 8
0xff00ff00, //div 16
0xffff0000, //div 32
};

However, this means that for 16KHz voice systems where the system MCLK is 24.576MHz (eg. if music playback is required), the required BCLK of 4.096MHz is not achievable as we need /6. We cannot even use a clock block in XS2 to get to this value as we can divide by 2n only and TDM master can minimum divide by 2.

It also means excessive instructions are used generating the BCLK.

Suggest either a divide by 1 option (as per USB audio) or preferably an XS2 friendly clock block divider derived BCLK ideally with a data frame transfer callback (all channels in a sample period) to further reduce overhead (As per i2s_frame_master)

[ed-xmos]

Addressed by i2s_frame_master. This will support any ratio that can be divided by a clock block (2n)