Hello, I am a student looking at your posts about Ethernet communication.
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The system I am trying to implement is to send the data stored in the FPGA block RAM to the PC via ethernet at a data rate of 100Mbps. The evaluation board I'm using is ML605. I know that it is different from the board you used, but if you change only ucf it will work the same. (I feel very grateful to you.) However, it looks like your post does not have main.vhd. I need a main entitiy which consists of several components for Ethernet communication. I can not see the file. Can I get the file?
In addition, you have framed the pad, CRC, etc. directly, why did you use IP_CORE provided by xilinx without using it?
Thank you.
Sincerely,
However, it looks like your post does not have main.vhd. I need a main entitiy which consists of several components for Ethernet communication. I can not see the file. Can I get the file?
You have to implement the top module yourself according to your application and requirements. An example is provided here: https://github.com/pkerling/ethernet_mac_test
In addition, you have framed the pad, CRC, etc. directly, why did you use IP_CORE provided by xilinx without using it?
I do not understand the question. What IP core are you referring to?
Thank you for your quick reply.
You are right.
I know I need to implement the top module for the system I want to design. However, because I want to analyze and modify your top module as a reference, I requested. Although your system and my system are different.
The second question implies why are you implement framing module.
Xilinx has already provided an IP CORE that automatically inserts preamble, SFD, Pad, and CRC.
Thank you.
Sincerely,
However, because I want to analyze and modify your top module as a reference, I requested.
OK, then please have a look at https://github.com/pkerling/ethernet_mac_test/blob/master/ethernet_mac_test.vhd
Xilinx has already provided an IP CORE that automatically inserts preamble, SFD, Pad, and CRC.
Please provide a link to the core you are referring to.
Thank you for your kindness.
And this is the link that I was said that : https://www.xilinx.com/search/site-keyword-search.html?searchKeywords=Virtex-6%20Ethernet%202.3, LogiCORE IP Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper v2.3 User Guide (AXI).
Could you reply some quesion?
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Why did you use std_ulogic and std_ulogic_vector?
Isn't a std_logic and std_logic_vector for latest version of that type? -
And, I tried running tb you posted but mii_tx_data comes out as UUUUUUUU.
If you look at the code, it seems that insert data to the PHY from a constant called t_memory. Is there anything else I need to do? -
If I want to combine a module that emits one bit every 100MHz into your Ethernet module and send it to PC at a 1000MHz clock, what parts should I focus on?
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Where can I find FPGA board's source-address? In case of destination address, It might seem that I can transmit x"FFFF" as broadcast but I don't have any information FPGA board's MAC address.
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I want to analyze all the code like mind but it is difficult to interpret because the whole flow is not understood. Your dissertation is also considered as a reference, but it seems to be inefficient. As a person who has a lot of understanding about Ethernet, can you please guide me to study Ethernet?
Thanks.
Sincerely,
And this is the link that I was said that : xilinx.com/search/site-keyword-search.html?searchKeywords=Virtex-6%20Ethernet%202.3, LogiCORE IP Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper v2.3 User Guide (AXI).
This is a fully-featured Ethernet MAC, i.e. it fulfills the same role as this project (albeit with major differences in goals and implementation - importantly, it is not open source, while this project is). So your question of why I did not use it in this MAC does not make any sense. You can use the TEMAC instead of this project, not in addition to or as part of.
Why did you use std_ulogic and std_ulogic_vector? Isn't a std_logic and std_logic_vector for latest version of that type?
Both are distinct types part of modern VHDL and none is "newer" than the other. std_ulogic - contrary to std_logic does not automatically resolve conflicts, which is often unintended. You can find more information about this on the internet and in VHDL textbooks.
And, I tried running tb you posted but mii_tx_data comes out as UUUUUUUU.
If you look at the code, it seems that insert data to the PHY from a constant called t_memory. Is there anything else I need to do?
How did you try to run the testbench exactly? Can you post full output?
If I want to combine a module that emits one bit every 100MHz into your Ethernet module and send it to PC at a 1000MHz clock, what parts should I focus on?
You should send a packet header to the TX fifo and then you can just pipe the values there as they come in (until the packet becomes too big).
Where can I find FPGA board's source-address? In case of destination address, It might seem that I can transmit x"FFFF" as broadcast but I don't have any information FPGA board's MAC address.
There is no MAC address assigned to a board, except if you have some demo/evaluation board and the manufacturer assigns one for you. Then you can usually read it out of an EEPROM. Otherwise you have to choose a MAC address yourself. You might want to read https://en.wikipedia.org/wiki/MAC_address
want to analyze all the code like mind but it is difficult to interpret because the whole flow is not understood. Your dissertation is also considered as a reference, but it seems to be inefficient. As a person who has a lot of understanding about Ethernet, can you please guide me to study Ethernet?
I'm sorry, I will not be able to give you a course on Ethernet here. I have referenced further resources and books in my thesis which you can use to learn more. This MAC is really intended for use by people that have a solid understanding of Ethernet technology and want to work at the lowest level. I think you should maybe consider other options, such as using a soft-core processor for sending the data.
No further communication, closing