yybbest's Stars
rishabv90/Asic-Design-Labratory
This contains the Labs in Verilog code
Evensgn/RISC-V-CPU
RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
sabbaghm/c-ll-verilog
An LLVM based mini-C to Verilog High-level Synthesis tool
Michaelvll/RISCV_CPU
A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL
kevinpt/symbolator
HDL symbol generator
cgerum/c2verilog
Inofficial version of c-to-verilog.com
m-labs/VexRiscv-verilog
Using VexRiscv without installing Scala
CospanDesign/verilog-visualizer
A GUI to help users visualize the structure of a verilog HDL project
cebarnes/cordic
An implementation of the CORDIC algorithm in Verilog.
SpinalHDL/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
dgsmith/Verilog-Simulator
A simulator for Verilog written in C++
cseed/cynth
a simple C-to-Verilog compiler
freecores/verilog_fixed_point_math_library
Fixed Point Math Library for Verilog
mshr-h/vscode-verilog-hdl-support
HDL support for VS Code
pro711/sublime-verilog
Verilog Package for Sublime Text 2/3
alexforencich/verilog-ethernet
Verilog Ethernet components for FPGA implementation
google/dopamine
Dopamine is a research framework for fast prototyping of reinforcement learning algorithms.
drichmond/riffa-development
The RIFFA development repository
farhanrahman/riffa
RIFFA (Reusable Integration Framework for FPGA Accelerators) is a framework developed in University of California, San Diego. This project utilises the RIFFA framework to define an interface to interact with a user's IP core on the FPGA to send and receive data to and from the PC. This particular project is being developed under Imperial College London.
freecores/pcie_sg_dma
PCIe SG DMA controller
enfiskutensykkel/ssd-gpu-dma
Build userspace NVMe drivers and storage applications with CUDA support
Chester-Gillon/nvram_uio
Experiment for creating a Linux UIO driver for a PCIe device with DMA
imjustadog/AE-PCIE-DMA-AXI
way to use xapp1052 with new version of PCIe IP core(AXI bus)
VerificationExcellence/SystemVerilogReference
training labs and examples
verilog-to-routing/vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
pabennett/chiptools
ChipTools is a utility to automate FPGA build and verification
udif/ctoverilog
A C to verilog compiler
etherzhhb/Shang
The Shang high-level synthesis framework
dawsonjon/Chips-2.0
FPGA Design Suite based on C to Verilog design flow.
open-mmlab/mmskeleton
A OpenMMLAB toolbox for human pose estimation, skeleton-based action recognition, and action synthesis.