Why RegFile can't be written？

[Deleted user]

I just submit the issue of Yang.
I wrote a tester for regfile. And I know RegWr should be set to 1 to enable reg file writing. Here is the tester.

class RegFileTests(c: RegFile) extends PeekPokeTester(c) {
	var tbusa = 0
	var tbusb = 0
    
	def asUInt(InInt: Int) = (BigInt(InInt >>> 1) << 1) + (InInt & 1)

	for (i <- 0 until 32){
		val tbusw  = i + 1000
		val tra    = i
        val trb    = 0
        val trw    = i
        val tregwr = 1

		poke(c.io.BusW, tbusw)
		poke(c.io.RA, tra)
		poke(c.io.RB, trb)
		poke(c.io.RW, trw)
	    poke(c.io.RegWr, tregwr)

		step(1)

	}
	for(i <- 0 until 32){
		val tbusw  = i + 1000
		val tra    = i
        val trb    = 0
        val trw    = i
        val tregwr = 0
        
        poke(c.io.RA, tra)
		poke(c.io.RB, trb)
        expect(c.io.BusA, i + 1000)
        expect(c.io.BusB, 1000)

        if( i== 30 ){
	    	poke(c.io.RegWr, 1)
	    	println(peek(c.io.RegWr)toString)

        	poke(c.io.BusW, 666)
        	printf("i=30\n")
        	println(peek(c.io.BusW)toString)

			poke(c.io.RW, 15)
			println(peek(c.io.RW)toString)

        }
        else if( i == 31 ){
        	printf("i=31\n")

        	poke(c.io.RB, 15)
        	println(peek(c.io.BusB)toString)

        	expect(c.io.BusB, 666)
        }
        printf("tra: %d tbusw: %d\n",tra,tbusw)
	}
}

The output of this tester raises a error:

Circuit state created
SEED 1494282266689
tra: 0 tbusw: 1000
tra: 1 tbusw: 1001
tra: 2 tbusw: 1002
tra: 3 tbusw: 1003
tra: 4 tbusw: 1004
tra: 5 tbusw: 1005
tra: 6 tbusw: 1006
tra: 7 tbusw: 1007
tra: 8 tbusw: 1008
tra: 9 tbusw: 1009
tra: 10 tbusw: 1010
tra: 11 tbusw: 1011
tra: 12 tbusw: 1012
tra: 13 tbusw: 1013
tra: 14 tbusw: 1014
tra: 15 tbusw: 1015
tra: 16 tbusw: 1016
tra: 17 tbusw: 1017
tra: 18 tbusw: 1018
tra: 19 tbusw: 1019
tra: 20 tbusw: 1020
tra: 21 tbusw: 1021
tra: 22 tbusw: 1022
tra: 23 tbusw: 1023
tra: 24 tbusw: 1024
tra: 25 tbusw: 1025
tra: 26 tbusw: 1026
tra: 27 tbusw: 1027
tra: 28 tbusw: 1028
tra: 29 tbusw: 1029
i=30
666
15
1
tra: 30 tbusw: 1030
i=31
1015
EXPECT AT 32   io_BusB got 1015 expected 666 FAIL
tra: 31 tbusw: 1031
test RegFile Success: 64 tests passed in 37 cycles taking 0.285850 seconds
RAN 32 CYCLES FAILED FIRST AT CYCLE 32
================================================================================
Errors: 1: in the following commands
ercesiMIPS RegFile: test error occurred
================================================================================

Exception: sbt.TrapExitSecurityException thrown from the UncaughtExceptionHandler in thread "run-main-0"
java.lang.RuntimeException: Nonzero exit code: 1
	at scala.sys.package$.error(package.scala:27)
[trace] Stack trace suppressed: run last test:runMain for the full output.
[error] (test:runMain) Nonzero exit code: 1
[error] Total time: 18 s, completed May 9, 2017 6:24:29 AM

Anyone tells me why the error happens?

[SYAAAA]

because in the second "for",I did't use "step",step is use to create clock, and for "Mem",you need a clock to write data in RegFile.

[zavs]

Yes, in RTL description, a register can only be write in the trigger edge the clock. So the register writing process will not be triggered until you set a valid clock cycle.