HIGH time and LOW time for the clock signal

[zeekhuge]

firmware code - https://github.com/ZeekHuge/BeagleScope/blob/port_to_4.4.12-ti-r31%2B/firmware/main_pru1_def.asm#L222
The clock signal being generated by the firmware code is in form of tiny pulses, as there is just one instruction gap between the two toggles

`TAKE_SAMPLE_8 .macro RX

    CLK_TOGGLE

    MOV RX, R31

    ;LDI    RX, FAKE_DATA

    CLK_TOGGLE

    .endm`

This may not work with all ADC as the timing characteristics change from converter to converter. The HIGH and LOW time of the clock signal should actually be configurable or at least should have around 50% duty cycle. This will help covering a larger number of converters.