zeroasiccorp/switchboard

Issues

• Hierarchy Simulation

  #255 opened 2 months ago by tthompsongmsi
  1

• Incompatibility with recent UMI repo commits

  #238 opened 3 months ago by sgherbst
  2

• SWITCHBOARD_SIM_PORT macro seems to be broken

  #233 opened 4 months ago by zephray
  2

• Auto-format integer constants used in tie-offs

  #232 opened 4 months ago by sgherbst
  0

• Clean up for single-netlist Verilog generation

  #231 opened 4 months ago by sgherbst
  0

• CPU affinity

  #224 opened 4 months ago by sgherbst
  0

• Approximate synchronization of simulation time for waveform comparisons

  #220 opened 5 months ago by sgherbst
  1

• SbNetwork: intf_defs collision when multiple instances of an SbDut have the same interface made external

  #219 opened 5 months ago by sgherbst
  0

• autowrap: be able to specify tieoffs as runtime parameters

  #218 opened 5 months ago by sgherbst
  0

• Support UMI packets with DW>256

  #217 opened 5 months ago by sgherbst
  0

• Mechanism for general interface connections in subnetworks

  #216 opened 5 months ago by sgherbst
  0

• Mechanism for declaring arrayed/bundled interfaces with autowrap

  #215 opened 5 months ago by sgherbst
  1

• Generic Switchboard launch flow

  #118 opened 5 months ago by sgherbst
  1

• Improve performance of TCP bridge

  #121 opened 5 months ago by sgherbst
  1

• Tool for inspecting queue files

  #131 opened 5 months ago by sgherbst
  0

• Implement "last" bit in switchboard/verilog/fpga/umi_fpga_queues.sv

  #150 opened 5 months ago by sgherbst
  0

• Implement "last" bit in switchboard/verilog/sim/umi_tx_sim.sv

  #151 opened 5 months ago by sgherbst
  0

• Extend random_packet to support address ranges

  #129 opened 5 months ago by sgherbst
  0

• perf_meas_sim: allow string printed to be customized

  #117 opened a year ago by sgherbst
  1

• "Verbose" mode

  #133 opened a year ago by sgherbst
  1

• BLKSEQ Warning in sb_rx_sim.sv and sb_tx_sim.sv

  #134 opened 5 months ago by sgherbst
  1

• When there is an alignment error, print out the data type detected to make debug easier

  #135 opened 5 months ago by sgherbst
  1

• create_cmdline feature

  #206 opened 5 months ago by sgherbst
  1

• Improve simulator shutdown behavior for regression tests

  #202 opened 7 months ago by sgherbst
  0

• Document "args" example and make self-checking

  #201 opened 7 months ago by sgherbst
  0

• Option to error out on UMI warnings

  #190 opened 8 months ago by sgherbst
  0

• TODOs in switchboard/cpp/switchboard_pcie.hpp

  #152 opened 8 months ago by sgherbst
  2

• Pass DW information automatically from Verilog modules to software interface

  #194 opened 8 months ago by sgherbst
  0

• Error when instantiating multiple TX/RX blocks with different values of DW

  #186 opened 8 months ago by sgherbst
  0

• Bug in AXI writer handshake

  #179 opened 10 months ago by dpetrisko
  1

• Provide a mechanism for retrieving TX/RX queue names from a UmiTxRx object

  #154 opened a year ago by sgherbst
  0

• Implement Switchboard "last" flag for UMI traffic

  #120 opened a year ago by sgherbst
  1

• Parameterizable Switchboard packet width

  #119 opened a year ago by sgherbst
  0

• Implement wstrb in switchboard/verilog/fpga/config_registers.sv

  #149 opened a year ago by sgherbst
  0

• Central definition of UMI parameters supported by switchboard

  #148 opened a year ago by sgherbst
  0

• Avoid copying data in python/switchboard_pybind.cc

  #147 opened a year ago by sgherbst
  0

• Perform checking in examples/fpga_loopback

  #146 opened a year ago by sgherbst
  0

• Support Windows

  #139 opened a year ago by sgherbst
  0

• Explore abstractions for testing UMI hosts

  #132 opened a year ago by sgherbst
  0

• Fix issue in perf_meas_sim when there is a drop in simulation speed

  #130 opened a year ago by sgherbst
  0

• Make it easier to validate queue name connections

  #128 opened a year ago by sgherbst
  0

• Review blocking behavior in Python API

  #127 opened a year ago by sgherbst
  0

• Comprehensive test of ready/valid signaling styles

  #126 opened a year ago by sgherbst
  0

• Explore more performant ways to expose many queues on FPGA

  #125 opened a year ago by sgherbst
  0

• Error out when building if Verilator version is incompatible

  #124 opened a year ago by sgherbst
  0

• Investigate setuptools_scm

  #123 opened a year ago by sgherbst
  0

• Add comment format checking to Verilog lint

  #122 opened a year ago by sgherbst
  0

• Maximum size for UMI transactions in the Python interface

  #55 opened 2 years ago by sgherbst
  1

• Provide access to FPGA config registers via Python

  #51 opened 2 years ago by nmoroze
  0

• Enable direct interaction with `PySbTxPcie`/`PySbRxPcie` queues

  #50 opened 2 years ago by nmoroze
  0