Bug in AXI writer handshake

[dpetrisko]

switchboard/switchboard/verilog/fpga/axi_writer.sv

Line 53 in 39010f0

STATE_WR_ADDR: begin

AXI subordinates are permitted to wait until (awvalid && wvalid) to raise (awready, wready). axi_writer will deadlock under this wait condition

[sgherbst]

Thanks for catching this issue! This will be fixed once #182 is merged.