Two request with same address are sent to mem within 100 cycles, which will makes mem think the second request should get it data from other caches.

Question

Two request with same address are sent to mem within 100 cycles, which will makes mem think the second request should get it data from other caches.

Closed this issue 6 years ago · 1 comments

Answer 1 · 2018-11-15T11:48:13.000Z

I add a new state(sending) for memory blocks. Memory block records the cache id which first requests this data. And each cycle, mem check the pipe to bus, if there is memory block in 'sending' status with cache id A, and there isn't any message in pipe sending to A and address equalling to that memory block, I change memory block to 'in cache'.