zyx7k
Junior Student & Undergraduate Researcher @ IIIT Hyderabad. Hobbyist Photographer.
Hyderabad, India.
Pinned Repositories
Analyzing-Hateful-Memes
Submission for Precog Recruitment Task 2: Analyzing Hateful Memes
ApexBody.github.io
StudentKit Testing
communication-theory-project
Implementing a full-fledged communication system for QPSK Modulation in MATLAB
course-material
Collection of Question Papers for various courses [UG2k22 IIIT-Hyderabad]
iiitprevpapers
IIIT Hyderabad Previous Paper Repo
Magic-Layout-4-Bit-ALU
Designing & Implementing a 4-Bit ALU in MAGIC Layout
Metro-Rail-Management-System
Developed a centralized database system for a modern urban metro network to enhance passenger services, operational efficiency, and strategic planning. Integrated elements like ticket booking, schedules, and station management to ensure seamless commuting and data-driven decision-making.
ngspice-4-Bit-ALU
Implementing a 4-Bit ALU in Ngspice
sample-verilog-codes
Sample Codes for Verilog.
Semester-3-Resources
Study Material for ECE curriculum - 3rd Semester
zyx7k's Repositories
zyx7k/course-material
Collection of Question Papers for various courses [UG2k22 IIIT-Hyderabad]
zyx7k/Analyzing-Hateful-Memes
Submission for Precog Recruitment Task 2: Analyzing Hateful Memes
zyx7k/ngspice-4-Bit-ALU
Implementing a 4-Bit ALU in Ngspice
zyx7k/Semester-3-Resources
Study Material for ECE curriculum - 3rd Semester
zyx7k/ApexBody.github.io
StudentKit Testing
zyx7k/communication-theory-project
Implementing a full-fledged communication system for QPSK Modulation in MATLAB
zyx7k/iiitprevpapers
IIIT Hyderabad Previous Paper Repo
zyx7k/Magic-Layout-4-Bit-ALU
Designing & Implementing a 4-Bit ALU in MAGIC Layout
zyx7k/Metro-Rail-Management-System
Developed a centralized database system for a modern urban metro network to enhance passenger services, operational efficiency, and strategic planning. Integrated elements like ticket booking, schedules, and station management to ensure seamless commuting and data-driven decision-making.
zyx7k/sample-verilog-codes
Sample Codes for Verilog.
zyx7k/Signal-Processing-Project
MATLAB Project Demonstrating Signal Processing Methods for Various Purposes
zyx7k/Verilog-4-Bit-ALU
Implementing a 4-Bit ALU in Verilog
zyx7k/Y86-64-Processor
Sequential & Pipelined implementation of Y86-64 ISA in Verilog
zyx7k/zyx7k