0xArt

Complex_Sinusoid_DDFS_Verilog

OpenRoverControllerAndroid

OpenRoverControllerArduino

OpenRoverControllerAVR

Parallel_Transposed_FIR_Filter_Verilog

Passe_Passe_Network_Switch

A FPGA layer 2 network switch with the unique ability of having virtual ports that can transmit and receive UDP data.

RGMII_Ethernet_Transceiver_Verilog

Verilog module to transmit/receive to/from RGMII compatible ethernet PHY

Super_SPI_Master_Verilog

SPI Master Verilog module

SuperHashProcessor

Quartus Prime project directory of a SHA1, SHA256, and MD5 hash processor written in System Verilog.

Tiny_But_Mighty_I2C_Master_Verilog

I2C Master Verilog module

0xArt/Tiny_But_Mighty_I2C_Master_Verilog

I2C Master Verilog module

0xArt/RGMII_Ethernet_Transceiver_Verilog

Verilog module to transmit/receive to/from RGMII compatible ethernet PHY

0xArt/Super_SPI_Master_Verilog

SPI Master Verilog module

0xArt/Passe_Passe_Network_Switch

A FPGA layer 2 network switch with the unique ability of having virtual ports that can transmit and receive UDP data.

0xArt/SuperHashProcessor

Quartus Prime project directory of a SHA1, SHA256, and MD5 hash processor written in System Verilog.

0xArt/Complex_Sinusoid_DDFS_Verilog

0xArt/OpenRoverControllerAndroid

0xArt/OpenRoverControllerArduino

0xArt/OpenRoverControllerAVR

0xArt/Parallel_Transposed_FIR_Filter_Verilog

0xArt/RaspberryPi_Servo_Control

0xArt/Sine_Generator_Verilog

0xArt/SystemVerilogUART

0xArt/CryptoANN

0xArt/PersonalSite

0xArt/Wave