/pipeline_processor_MIPS

MIPS Pipeline Processor written in verilog

Primary LanguageVerilog

CSN-221 Project- Pipeline Processor

Basic 5 stage pipelined processor based on 32-bit MIPS Instruction Set using 'VERILOG'.

The various units such as instruction fetch, instruction decode etc. are implemented as different modules. These modules are then integrated in the top level module.