Engineered with half-adders and full-adders for efficiency. Size is variable with parameter values, leaving it field-programmable for engineers who wish to use in FPGAs.
The ASIC showcased in the report is a 64-bit implementation with over 13000 leaf cells.
Please refer to the report for power, timing, and area analyses. The _SIM.v files contain testbenches to simulate each of the modules.