/downsampling_processor_fpga

[2018] A custom processor, ISA and implement an algorithm to filter and downsample a given image and implement it on an Altera de2-115. Additional credit is given for implementation of a cache memory and DSP functionalities.

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Custom Processer Design and Implementation on Altera de2-115 to Downsample an Image

The task is to design a custom processor, an ISA and develop the assembly code to filter and downsample a given image and implement it on an Altera de2-115. Additional credit is given for implementation of a cache memory and DSP functionalities.