Coreblocks is an experimental, modular out-of-order RISC-V core generator implemented in Amaranth. Its design goals are:
- Simplicity. Coreblocks is an academic project, accessible to students. It should be suitable for teaching essentials of out-of-order architectures.
- Modularity. We want to be able to easily experiment with the core by adding, replacing and modifying modules without changing the source too much. For this goal, we designed a transaction system called Transactron, which is inspired by Bluespec.
- Fine-grained testing. Outside of the integration tests for the full core, modules are tested individually. This is to support an agile style of development.
In the future, we would like to achieve the following goals:
- Performance (up to a point, on FPGAs). We would like Coreblocks not to be too sluggish, without compromising the simplicity goal. We don't wish to compete with high performance cores like BOOM though.
- Wide RISC-V support. The core can currently run Zephyr and a MMU-less Linux kernel. Running a fully-featured Linux core in supervisor mode is our next target.
The core currently supports the full unprivileged RV32I instruction set and a number of extensions, including:
- M - integer multiplication and division, with Zmmul only as an option,
- A - atomic instructions, comprising of Zaamo and Zalrsc (without multi-core support),
- C - compressed instructions,
- B - bit manipulation, comprising of Zba, Zbb and Zbs, extension Zbc is implemented too.
Machine mode is fully implemented. Support for supervisor mode is currently missing.
Coreblocks can be easily integrated with LiteX SoC generator.
The documentation for our project is automatically generated using Sphinx.
Resource usage and maximum clock frequency is automatically measured and recorded.
Set up the development environment following the project documentation.
External contributors are welcome to submit pull requests for simple contributions directly. For larger changes, please discuss your plans with us through the issues page or the discussions page first. This way, you can ensure that the contribution fits the project and will be merged sooner.
Copyright © 2022-2025, University of Wrocław.
This project is three-clause BSD licensed.