Well organized Verilog codes can be integrated to any project
-
ip_fifo_ctrl_rtl.v: Sync/Async FIFO controller.
-
ip_sincos_gen_rtl.v: Sine, Cosine function generator by single-stage Modified CORDIC method.
-
ip_spi_m_rtl.v: A SPI Master
-
ip_pwr2_rtl.v: Power of 2 calculation by muli-cycle operation
-
ip_log2int_rtl.v: integer-part of Log2 calculation by muli-cycle operation
-
ip_vtm_rtl.v: Native video timing generator frame start, frame end, horizontal line start/end, href
-
gm_curve_rtl.v: Gamma correction and user defined curve. Bending strength of the curve is adjustable by 16 index.
axi
-
ip_v2axi4s_m_rtl.v: Native video to AXI4-stream master conversion
-
ip_axi4s2v_s_rtl.v: AXI4-stream slave to native video conversion
parking-guide-line: A design to draw color, transparency, angle, and line width programmable parking guide line.
cu: Calculation unit of basic arithmetic operation