Pinned Repositories
fpga-dcn-kws
FPGA Implementation of the proposed model in master thesis.
Open-Source-IPs
PAAS_V1.0
PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
RFNoC-HLS-NeuralNet
rosetta
Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
Tiny_YOLO_v3_ZYNQ
Implement Tiny YOLO v3 on ZYNQ
vivado-hls-broadcast-optimization
[DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
Yolov2-FPGA-CNN-
Zynq_HLS_DDR_Dataflow_kernel_2mm
This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation
zynqnet
Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"
3i-hust-fpga's Repositories
3i-hust-fpga/fpga-dcn-kws
FPGA Implementation of the proposed model in master thesis.
3i-hust-fpga/Open-Source-IPs
3i-hust-fpga/PAAS_V1.0
PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
3i-hust-fpga/RFNoC-HLS-NeuralNet
3i-hust-fpga/rosetta
Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
3i-hust-fpga/Tiny_YOLO_v3_ZYNQ
Implement Tiny YOLO v3 on ZYNQ
3i-hust-fpga/vivado-hls-broadcast-optimization
[DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
3i-hust-fpga/Yolov2-FPGA-CNN-
3i-hust-fpga/Zynq_HLS_DDR_Dataflow_kernel_2mm
This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation
3i-hust-fpga/zynqnet
Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"
3i-hust-fpga/C-LSTM
3i-hust-fpga/CLINK
Compact LSTM inference kernel (CLINK) designed in C/HLS for FPGA implementation.
3i-hust-fpga/DeepLearningOnFpga
3i-hust-fpga/hls4ml
Machine learning in FPGAs using HLS
3i-hust-fpga/HLS_BLSTM
The community version of HLS_BLSTM (A BLSTM FPGA accelerator of an OCR appilcation, using CAPI/SNAP))
3i-hust-fpga/Light-HLS
Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation.
3i-hust-fpga/LSTM-PYNQ
3i-hust-fpga/netscope
Neural network visualizer
3i-hust-fpga/Open-Source-IPs-1