/matrix_mul_fyp

Reproduce a linear array architecture dealing with arbitrary-size matrix multiplication.

Primary LanguageSystemVerilog

matrix_mul_fyp

Reproduce a linear array architecture dealing with arbitrary-size matrix multiplication.

This project is for my final-year-project, Bachelor of Engineering. All I have coded is just for fun, DO NOT take it serious.😅

Spec

Design totally contains 15 pipeline stages.

Top Module

  • TA and TB Load CTL
  • MAC pipeline
  • TC Local Memory CTL