SCHEDULE

DESCRIPTION

4-bit Digital Lock (implemented in Verilog, SystemVerilog, and vHDL for comparison)
Lock-bypassing HW-trojan injection (if trojan activates, then the lock bypasses key if submission has a '1' bit in the 1st position).
3rd-party AES encryption (implemented in Verilog)
Encryption key-leaking HW-trojan injection (for a more advanced example)

Verilog
Pencil/Paper
Xilinx Vivado (on AWS Windows 11 Workspace intance)
EDA Playground (for prototyping and demonstration of wave analysis triggered by testbench)
Markdown (docs)
Pages (diagrams)

Handwrite original Digital Lock logic.
Simplify Digital Lock logic using Karnaugh Map.
Write original Digital Logic in Verilog, SystemVerilog, and vHDL.
Demonstrate the HW-trojan in action by showing how it can leak the passkey to a connected peripheral device given a different input.
Explain other advanced injection methods (e.g. using photoresistant ion-based doping mask phase of fabrication to sneakily increase required voltage thresholds between specified benign pre-existing or added circuits by creating vacancies for positive flow or adding electrons for negative flow, allowing the activation of the trojan by passing a custom voltage).
Explain pre and post injection mitigations now and in the future (e.g. NVC Quantum Sensor for precise electromagnetic difference scanning).
Demonstrate a more advanced info-leaking HW-trojan injection in AES cipher.