This Repository contains all required design files, plots and presentation for our VLSI Architecture Design Course Project which was an implementation of the IEEE Paper "A Highly Efficient Conditional Feedthrough Pulsed Flip-Flop for High-Speed Applications" by "Dashan Pan , Chao Ma, Lanqi Cheng, and Hao Min , Member, IEEE"
Paper: D. Pan, C. Ma, L. Cheng and H. Min, "A Highly Efficient Conditional Feedthrough Pulsed Flip-Flop for High-Speed Applications," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 1, pp. 243-251, Jan. 2020, doi: 10.1109/TVLSI.2019.2934899.
Group Members:
IMT2020503: Arhant Arora
IMT2020532: Anwit Suhas Damale
IMT2020536: Yugaan Mangesh Hagargi
IMT2020537: Yash Dharmesh Mogal