/RISC-V-Core

RISC-V core for FPGA

Primary LanguageShellMIT LicenseMIT

RISC-V-Core

  • RISC-V core for FPGA (Decided to run test for now, instead of directly running in the physical hardware or run it on hardware simulator)
  • Uses Harvard Computer architecture (might add Von neumann arch later)

Planned for later

  • Add the pipeline process for the Instruction (for now I'm just gonna execute the intruction in sequential order)