AI-Vector-Accelerator/ava-core
A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
SystemVerilogNOASSERTION
Issues
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Vsetvl Instruction
#1 opened by HamzaShabbir517
A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
SystemVerilogNOASSERTION