- Ibex: https://github.com/lowRISC/ibex
- opentitan: https://github.com/lowRISC/opentitan
- nvdla: https://github.com/nvdla/hw
- riscv-dv: https://github.com/google/riscv-dv
- core-v-verif: https://github.com/openhwgroup/core-v-verif
- openhmc: https://github.com/unihd-cag/openhmc
- riscv-vip: https://github.com/jerralph/riscv-vip
- ISP-UVM: https://github.com/nelsoncsc/ISP_UVM
- apb-vip-uvm: https://github.com/zhangyl4991/apb-vip-uvm
- axi-uvm: https://github.com/marcoz001/axi-uvm
- tvip-axi: https://github.com/taichi-ishitani/tvip-axi
- i2c-vip-uvm: https://github.com/zhangyl4991/i2c-vip-uvm
- tnoc: https://github.com/taichi-ishitani/tnoc
- SDRAM-Verification: https://github.com/yvnr4you/SDRAM-Verification
- Cores-SweRV: https://github.com/chipsalliance/Cores-SweRV
- e200_opensource: https://github.com/SI-RISCV/e200_opensource
- ariane: https://github.com/pulp-platform/ariane
- rsd: https://github.com/rsd-devel/rsd
- ultraembedded_riscv: https://github.com/ultraembedded/riscv
- ultraembedded_ipcores: https://github.com/ultraembedded/cores
- schoolMIPS: https://github.com/MIPSfpga/schoolMIPS
- patmos: https://github.com/t-crest/patmos
- verilog-pcie: https://github.com/alexforencich/verilog-pcie
- verilog-axi: https://github.com/alexforencich/verilog-axi
- wb2axi: https://github.com/ZipCPU/wb2axip
- alice5: https://github.com/bradgrantham/alice5
- Soclib: http://www.soclib.fr/trac/dev
- Gem5: http://www.m5sim.org/Main_Page