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AdriftXCore
FPGA/IC designer
Location:
China
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AdriftXCore GitHub
6
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Pinned Repositories
AdriftXCore
My personal repository
0
0
ddr_interface
ddr interface
Language:
Verilog
0
0
hdmi_interface
Language:
Verilog
0
0
SIMENV
Language:
SystemVerilog
0
0
verilog-pcie
Language:
SystemVerilog
0
1
0
0
Xilinx_lowlatencyPCMPCS
Language:
VHDL
0
0
AdriftXCore's Repositories
AdriftXCore/
AdriftXCore
My personal repository
0
0
AdriftXCore/
ddr_interface
ddr interface
Language:
Verilog
0
0
AdriftXCore/
hdmi_interface
Language:
Verilog
0
0
AdriftXCore/
SIMENV
Language:
SystemVerilog
0
0
AdriftXCore/
verilog-pcie
Language:
SystemVerilog
0
1
0
0
AdriftXCore/
Xilinx_lowlatencyPCMPCS
Language:
VHDL
0
0