Ahmed0100

Pinned Repositories

• aes_cipher_decipher_hls_sc

  aes_cipher_decipher_hls_sc

  Language:C++00

• aes_cipher_hls_sc

  aes_cipher_hls_sc

  Language:C++00

• ahb_memory_slave_vip

  ahb_memory_slave_vip

  Language:SystemVerilog10

• amba_apb_ip

  AMBA APB protocol IP

  Language:Verilog00

• auto_neural_network_generation_python

  Automatic generation of neural network RTL Verilog files, weights & biases memory files, and wrapping everything in Xilinx Vivado project using Python.

  Language:Verilog11

• fft_ip_hls_soc

  Language:C++10

• full_pong_game_vga_fpga

  full_ping_pong_game_vga_fpga

  Language:Verilog20

• logic_analyzer_vga_fpga_v1_0

  logic_analyzer_vga_fpga_v1_0

  Language:SystemVerilog10

• processor_uart_system_synopsys

  processor_uart_system_synopsys

  Language:Verilog10

• spatial_filter_line_buffer_verilog_ip_soc

  Language:VHDL10

Ahmed0100's Repositories