Shift register test
Avg number of clock cycles to shift the pointer location and send the preceeding data to the shift register = 3 cycles
There is anamoly in the start, which might be due to cache not kicking in on the HPS side on the first clock
Avg number of clock cycles to shift the pointer location and send the preceeding data to the shift register = 3 cycles
There is anamoly in the start, which might be due to cache not kicking in on the HPS side on the first clock