AkshayRaj/MIPS_PipeLine_Simulator

This Project simulates the workings of a 4 stage MIPS PipeLine. The Simulator writes the Cycle Number when an instruction leaves a PipeLine Stage. It detects RAW, WAW, WAR and Structural Hazards Accurately. A two level Memory Hierarchy is also implemented in the PipeLine. Cache hits and Misses for both I-Cache and D-Cache are also written on the Scoreboard.

Java