AleksandarLilic

AES-256_hardware_design

VHDL design of the AES-256 encryption algorithm

AES-256_UVM

UVM testbench for AES-256 VHDL design

ama-riscv

Verilog implementation of RISC-V RV32I ISA

ama-riscv-perfsim

Cycle Accurate C++ performance model of the ama-riscv core

ama-riscv-sim

Instruction Set Simulator for RISC-V RV32I in C++

BitNetMCU

Neural Networks with low bit weights on a CH32V003 RISC-V Microcontroller without multiplication

ch32v003fun

An open source software development stack for the CH32V003 10¢ 48 MHz RISC-V Microcontroller - as well as many other chips within the ch32v/x line.

Concurrent_Java

Cyclone_II_SoPC

VHDL hardware accelerators on Cyclone II FPGA with MCU apps in C for Nios II core

LPC1768_development

CMSIS-RTOS2, driver development and data acquisition application on NXP LPC1768

AleksandarLilic/Cyclone_II_SoPC

VHDL hardware accelerators on Cyclone II FPGA with MCU apps in C for Nios II core

AleksandarLilic/LPC1768_development

CMSIS-RTOS2, driver development and data acquisition application on NXP LPC1768

AleksandarLilic/AES-256_hardware_design

VHDL design of the AES-256 encryption algorithm

AleksandarLilic/AES-256_UVM

UVM testbench for AES-256 VHDL design

AleksandarLilic/ama-riscv

Verilog implementation of RISC-V RV32I ISA

AleksandarLilic/ama-riscv-perfsim

Cycle Accurate C++ performance model of the ama-riscv core

AleksandarLilic/ama-riscv-sim

Instruction Set Simulator for RISC-V RV32I in C++

AleksandarLilic/BitNetMCU

Neural Networks with low bit weights on a CH32V003 RISC-V Microcontroller without multiplication

AleksandarLilic/ch32v003fun

An open source software development stack for the CH32V003 10¢ 48 MHz RISC-V Microcontroller - as well as many other chips within the ch32v/x line.

AleksandarLilic/Concurrent_Java

AleksandarLilic/mini-rv32ima

A tiny C header-only risc-v emulator.

AleksandarLilic/tiny-AES-c

Small portable AES128/192/256 in C