Alenkruth
Computer Engineering PhD student at The University of Virginia. I work on Computer Architecture, Hardware Security, and RTL design and verification
University of VirginiaCharlottesville, VA.
Pinned Repositories
AESCore
AES core capable of performing AES 256 Encryption in CTR/GCM modes.
alenkruth.github.io
My Personal Website.
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Coursera-HDL-for-FPGAs
Solutions to the Assignments
crc_accelerator
A parameterizable CRC accelerator written in System Verilog.
Crypto_RI5CY
RI5CY from the PULP Platform modified to support Crypto instructions [Work in Progress]
FireMarshal
Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
Gem5McPatParser
Gem5 to McPAT parser with multicore and cache support
riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
uatg
Alenkruth's Repositories
Alenkruth/Coursera-HDL-for-FPGAs
Solutions to the Assignments
Alenkruth/Crypto_RI5CY
RI5CY from the PULP Platform modified to support Crypto instructions [Work in Progress]
Alenkruth/AESCore
AES core capable of performing AES 256 Encryption in CTR/GCM modes.
Alenkruth/Gem5McPatParser
Gem5 to McPAT parser with multicore and cache support
Alenkruth/alenkruth.github.io
My Personal Website.
Alenkruth/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Alenkruth/crc_accelerator
A parameterizable CRC accelerator written in System Verilog.
Alenkruth/FireMarshal
Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
Alenkruth/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
Alenkruth/riscv-isa-sim
Spike, a RISC-V ISA Simulator
Alenkruth/river_core_plugins
Alenkruth/rocket-chip
Rocket Chip Generator
Alenkruth/value_predictor
Value predictor built for the CS6354 course