Interchange formats for chip design.
Vlsir defines data schema for integrated circuit (IC) circuits, layouts, and simulations, using Google's Protocol Buffer schema definition language.
The name Vlsir is a merger of VLSI (very large scale integration - a way-outdated chip-world acronym) and IR (intermediate representation - the term every cool-kid copying compiler designers uses nowadays).
All of Vlsir's schema-definitions live in the protos directory.
| Schema | Description |
|---|---|
| Circuit | Circuit / Hardware Descriptions |
| Raw Layout | "Raw Polygon" IC Layout |
| Tetris Layout | "Tetris" Gridded IC Layout |
| Spice | Spice-Class Simulator Interface |
| Utilities | Shared Utilities |
Vlsir defines a data schema, which related projects use in code. Projects using vlsir can be written in any language with protobuf-compiler bindings - which includes essentially every popular programming language. Existing projects have prominently used Python, C++, and Rust. Bindings to each language are distributed through their language-specific package managers.
| Language | Bindings Package | Compiler |
|---|---|---|
| Python | https://pypi.org/project/vlsir/ | Google protoc |
| Rust | https://crates.io/crates/vlsir | Prost |
| JavaScript | (Coming Soon!) | protobuf.js |
The Vlsir repository also serves as home for the Python-language VlsirTools package.
VlsirTools is a collection of tools for working with Vlsir's schema, including:
- Netlisting to industry-standard formats (SPICE, Verilog, etc.)
- Drivers and result-parsers for Spice-class simulators
Run scripts/build.sh from the root directory of this repository.
git clone git@github.com:Vlsir/Vlsir
cd Vlsir
scripts/build.sh
Ongoing, co-developed projects which use vlsir:
| Project | Description | Language |
|---|---|---|
| Hdl21 | Generator-Based Hardware Description Library | Python |
| Layout21 | Multi-Layered Layout-Programming | Rust |
| BFG | Layout Generation for Open-Source FPGAs | C++ |