Alonger1988's Stars
jm2000/RISCV-FPU
Basic floating-point components for RISC-V processors
dawsonjon/fpu
synthesiseable ieee 754 floating point library in verilog
mortbopet/Ripes
A graphical processor simulator and assembly editor for the RISC-V ISA
mit-pdos/xv6-riscv
Xv6 for RISC-V
alexforencich/verilog-axi
Verilog AXI components for FPGA implementation
alexforencich/cocotbext-axi
AXI interface modules for Cocotb
alexforencich/verilog-i2c
Verilog I2C interface for FPGA implementation
openai/gym
A toolkit for developing and comparing reinforcement learning algorithms.
freecores/irda
IrDA
freecores/turbo8051
turbo 8051
riscv-mcu/hbird-sdk
OpenSource HummingBird RISC-V Software Development Kit
riscv-mcu/e203_hbirdv2
The Ultra-Low Power RISC-V Core
SI-RISCV/hbird-e-sdk
Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/
SI-RISCV/e200_opensource
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
276921237/pcie_rgmii
PCIE网卡项目，实现网口数据精确时间戳上报
chsasank/ARM7
Implemetation of pipelined ARM7TDMI processor in Verilog
PulseRain/Reindeer
PulseRain Reindeer - RISCV RV32I[M] Soft CPU
PulseRain/Reindeer_Step
Reindeer Soft CPU for Step CYC10 FPGA board
git/git
Git Source Code Mirror - This is a publish-only repository but pull requests can be turned into patches to the mailing list via GitGitGadget (https://gitgitgadget.github.io/). Please follow Documentation/SubmittingPatches procedure for any of your improvements.
vlang/v
Simple, fast, safe, compiled language for developing maintainable software. Compiles itself in <1s with zero library dependencies. Supports automatic C => V translation. https://vlang.io
Xilinx/linux-xlnx
The official Linux kernel from Xilinx
Xilinx/u-boot-xlnx
The official Xilinx u-boot repository
Xilinx/FPGA_as_a_Service
TheAlgorithms/C
Collection of various algorithms in mathematics, machine learning, computer science, physics, etc implemented in C for educational purposes.
TheAlgorithms/Python
All Algorithms implemented in Python