AmiraKhalid04/AES-Verilog

Verilog

Advanced Encryption Standard 🔑

This repository contains a Verilog implementation of the Advanced Encryption Standard (AES) offering:

Encryption & Decryption: Securely encrypts and decrypts data.
Configurable Key Size: Adapts to your security needs (128, 192, or 256 bits).

Getting Started

Clone the Repository First

For Simulation:

Simulate the design using a ModelSim (image of simulation to be added)

For FPGA Implementation:

Integrate the code into Quartus for deployment on Intel FPGAs.

Video (to be added)

The last 2 bytes at each round during both encryption and decryption are displayed on the 7 segment
When input text is encrypted and decrypted successfully the led turns on

Team members

_{Mohamed Kamal}

_{Amira Khaled}