/Multi-Cycle-CPU

A VHDL implementation of a multi cycle CPU w/ MMU, FSM, Decoder, Sequencer, ALU and Memory

Primary LanguageVHDL

Multi-Cycle-CPU

Consult the design document for a full breakdown of the functionality of this multi-cycle single ALU processor design. A test program is loaded into the generated memory, from a coe file. This can be modified using the instruction set detailed in the excel document to execute new programs.

Designed with love and care (and https://www.youtube.com/watch?v=6FEDrU85FLE) by Michael O'Donnell and Amrik Sadhra