Pinned Repositories
blackboxwm
A window manager for X11
bootrom
BootROM for JCore J2 SoCs
checkout
Action for checking out a repo
Cores-SweRV
SweRV EH1 core
Cores-SweRV-EH2
Cores-SweRV-EL2
SweRV EL2 Core
Cores-SweRV_fpga
jcore-cpu
J-Core J2/J32 5 stage pipeline CPU core
openlane
OpenLANE is an automated RTL to GDSII flow based on several components including OpenRoad, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
QM_XC6SLX16_DDR3
AndrewSftD's Repositories
AndrewSftD/blackboxwm
A window manager for X11
AndrewSftD/bootrom
BootROM for JCore J2 SoCs
AndrewSftD/checkout
Action for checking out a repo
AndrewSftD/Cores-SweRV
SweRV EH1 core
AndrewSftD/Cores-SweRV-EH2
AndrewSftD/Cores-SweRV-EL2
SweRV EL2 Core
AndrewSftD/Cores-SweRV_fpga
AndrewSftD/jcore-cpu
J-Core J2/J32 5 stage pipeline CPU core
AndrewSftD/openlane
OpenLANE is an automated RTL to GDSII flow based on several components including OpenRoad, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
AndrewSftD/QM_XC6SLX16_DDR3
AndrewSftD/QM_XC7A35T_DDR3
Xilinx Artix-7 FPGA Development Board
AndrewSftD/raven-picorv32
Silicon-validated SoC implementation of the PicoSoc/PicoRV32