Pinned Repositories
DDR3-Notes
My notes for DDR3 SDRAM controller
FPGA_Book_Experiments
My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
FPGA_OV7670_Camera_Interface
Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps
FPGA_RealTime_and_Static_Sobel_Edge_Detection
Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images
FPGA_SDRAM_Controller
SDRAM controller optimized to a memory bandwidth of 316MB/s
OpenLANE-Sky130-Physical-Design-Workshop
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
RISC-V
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
UberDDR3
Opensource DDR3 Controller
ULX3S_FPGA_Camera_Streaming
Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board
ULX3S_FPGA_Sobel_Edge_Detection_OV7670
Verilog design files and Icestudio file for Sobel Edge Detection with OV7670 camera using ULX3S FPGA Board
AngeloJacobo's Repositories
AngeloJacobo/UberDDR3
Opensource DDR3 Controller
AngeloJacobo/FPGA_Book_Experiments
My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
AngeloJacobo/RISC-V
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
AngeloJacobo/FPGA_OV7670_Camera_Interface
Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps
AngeloJacobo/OpenLANE-Sky130-Physical-Design-Workshop
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
AngeloJacobo/FPGA_RealTime_and_Static_Sobel_Edge_Detection
Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images
AngeloJacobo/DDR3-Notes
My notes for DDR3 SDRAM controller
AngeloJacobo/FPGA_SDRAM_Controller
SDRAM controller optimized to a memory bandwidth of 316MB/s
AngeloJacobo/ULX3S_FPGA_Camera_Streaming
Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board
AngeloJacobo/ULX3S_FPGA_Sobel_Edge_Detection_OV7670
Verilog design files and Icestudio file for Sobel Edge Detection with OV7670 camera using ULX3S FPGA Board
AngeloJacobo/FPGA_Asynchronous_FIFO
FIFO implementation with different clock domains for read and write.
AngeloJacobo/FPGA_I2C_Implementation
Bit-bang i2c protocol for interfacing with DS1307 RTC
AngeloJacobo/Customize-Android-Apps
This contains my notes on how to customize existing Android apps such as changing app name, app icon, hiding app from the app drawer, and others.
AngeloJacobo/DDR
A simple DDR3 memory controller
AngeloJacobo/ddr3-controller
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
AngeloJacobo/Hamming-ECC
Hamming ECC Encoder and Decoder to protect memories
AngeloJacobo/icestudio-examples
:snowflake: Icestudio examples - Community contributions
AngeloJacobo/Python_Scripts
Just a collection of my python scripts
AngeloJacobo/SDCard_Driver_Test
Vivado files for testing my SD card driver. Implemented on CMOD S7 FPGA.
AngeloJacobo/vsdstdcelldesign
This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an openlane flow.
AngeloJacobo/AngeloJacobo
Config files for my GitHub profile.
AngeloJacobo/demo-projects
Demo projects for various Kintex FPGA boards
AngeloJacobo/eth10g
10Gb Ethernet Switch
AngeloJacobo/iob-clint
AngeloJacobo/rtl
temporary repo
AngeloJacobo/zipstormmx
ZipSTORM-MX, an iCE40 ZipCPU demonstration project