AniketBadhan

AXI-VIP-Development

Cache

VHDL code for 32-bit Cache

Canny-Edge-Detection

RTL Code for Canny Edge Detection

Convolutional-Neural-Network

Implementation of CNN using Verilog

Ethernet-packet-Loopback-design-verification

Ethernet packet loopback design verification using SystemVerilog

FPGA-PC-communication-using-UART

Using UART communication between PC and FPGA to convert a colored image to black and white on FPGA

Memory-Controller-Verification

Functional Verification of Memory Controller

Microarchitecture-for-ALU

Microarchitecture for ALU

Pattern-Detector

Different types of FSMs for pattern detection

Scene-Recognition-Using-CNN-SVM-and-Perceptron

An MPI-based framework for parallel implementation of scene recognition using CNN as feature extractor and One Versus ALL SVM and Multiclass Perceptron as classifiers. Framework was tested on Bluewave cluster.

AniketBadhan/Convolutional-Neural-Network

Implementation of CNN using Verilog

AniketBadhan/Canny-Edge-Detection

RTL Code for Canny Edge Detection

AniketBadhan/AXI-VIP-Development

AniketBadhan/FPGA-PC-communication-using-UART

Using UART communication between PC and FPGA to convert a colored image to black and white on FPGA

AniketBadhan/Ethernet-packet-Loopback-design-verification

Ethernet packet loopback design verification using SystemVerilog

AniketBadhan/Memory-Controller-Verification

Functional Verification of Memory Controller

AniketBadhan/Microarchitecture-for-ALU

Microarchitecture for ALU

AniketBadhan/Pattern-Detector

Different types of FSMs for pattern detection

AniketBadhan/Cache

VHDL code for 32-bit Cache

AniketBadhan/Scene-Recognition-Using-CNN-SVM-and-Perceptron

An MPI-based framework for parallel implementation of scene recognition using CNN as feature extractor and One Versus ALL SVM and Multiclass Perceptron as classifiers. Framework was tested on Bluewave cluster.